Controlled impedance is one of those requirements that shows up as a single line on a fabrication drawing — "90 ohms differential ±10%" — and gets treated as something the fab house handles. In reality, impedance is a property of your stack-up, your trace geometry and your reference plane, and it has to be designed in before layout starts, not requested after.
The first decision is stack-up: dielectric thickness and copper weight between your signal layer and its reference plane set the baseline impedance for a given trace width. Change your stack-up after routing is complete and every high-speed trace on the board needs to be re-verified, sometimes re-routed. This is why we calculate target trace widths against the fab's actual dielectric constant and thickness tolerances before any placement begins.
The second is reference plane continuity. A differential pair routed cleanly across a split in its reference plane will still fail signal integrity — the return current has no continuous path, and you get impedance discontinuities and increased EMI exactly at the split. This is one of the most common high-speed layout mistakes we see in boards handed to us for revision: routing looks clean in 2D, but the return path was never considered.
Third, vias are not free. Every via a high-speed signal passes through introduces an impedance discontinuity from the unused stub and the change in reference plane. For high-speed nets, we either eliminate unnecessary layer transitions, use back-drilling to remove via stubs, or add ground stitching vias near the signal via to give return current a short path across the layer transition.
Getting this right is not about a fancier simulation tool — it is about sequencing the design process so stack-up, reference planes and via strategy are decided before routing, not fixed afterward.